Conventional methods of producing ferroelectric polymer memory devices (FPMDs) have a number of disadvantages that limit the quality and complexity of such devices. One method of producing FPMDs employs subtractive metal patterning techniques as known in the art. Such techniques introduce a high level of non-planarity to the substrate of the device and limit the patterning process as the number of layers of the device is increased.
A FPMD consists generally of a bottom electrode and a top electrode, both made of metal, having a ferroelectric polymer film (FPF) between them. An FPF is made of a polymer having the property of spontaneous electric polarization that can be reversed by application of an electric field. It is the FPF that constitutes the core of the memory bit for the FPMD. The difficulty of manufacturing FPMDs lies in patterning the electrodes without damaging or degrading the FPF in any way, and especially in not degrading the FPF in regard to its ferroelectric properties.
FIG. 1 illustrates a process employing a subtractive metal patterning technique in the context of FPMD production in accordance with the prior art. Process 100, shown in FIG. 1, begins at operation 105 in which a bottom electrode of a FPMD is formed on a substrate using a conventional subtractive metal patterning technique.
At operation 110 a layer of FPF is deposited upon the bottom electrode. The FPF is an extremely delicate material and can be easily degraded.
At operation 115 a metal (e.g., aluminum) layer is deposited upon the FPF to form the top electrode of the FPMD. Using subtractive metal patterning, the metal is deposited over the entire FPF layer, there is no ability to deposit the metal selectively.
At operation 120 the metal layer is etched using a resist mask to expose those areas to be etched and mask the desired pattern. The etching process is problematic for the production of FPMDs because the etching chemistry is typically very harsh and can degrade the FPF. For example, a typical aluminum etching employs a chlorine-based etchant that can have serious detrimental effects upon the ferroelectric properties of the FPF.
Moreover, to avoid corrosion of the metal layer, typical subtractive metal patterning techniques employ a significant amount of etch residues to protect the metal layer. These etch residues are difficult to remove, so cleaning up the metal layer is neither easy nor inexpensive.
Another important drawback of using a subtractive metal patterning process to produce FPMDs is the resultant non-planarity of the wafer surface.
FPMDs typically are constructed having 10-14 layers of metallization, or more. Prior art production techniques, including subtractive metal patterning introduce a non-planarity at each metallization layer. The cumulative effective of this non-planarity is that it becomes increasingly difficult to pattern at the upper layers. The increasing non-planarity of the wafer has a detrimental impact on the lithography and etch steps of metal patterning by reducing the process window. The non-planarity introduced through such techniques is typically greater than 30%.
For these and other reasons the production of FPMDs is limited by using non-optimal conventional metallization techniques such as subtractive metal patterning. Currently there is no cost-efficient method for producing FPMDs having a relatively large number of layers (i.e., ten or more layers).